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Intel engineers this week published new Linux open-source driver code for TPMI, the Topology Aware Register and PM Capsule Interface. Intel TPMI for seemingly future processors will allow for more streamlined power management handling and other enhancements over the way the Intel power management drivers currently function.
Intel’s Topology Aware Register and PM Capsule Interface (TPMI) is described as being a flexible, extendable, and PCIe-enumerable MMIO interface for power management features. Those features are currently focused around Intel Speed Select Technology (SST), Running-Average Power Limiting (RAPL), and Intel Uncore frequency scaling.
Making use of the Intel TPMI by the Speed Select driver code allows replacing all the existing mailbox commands with direct MMIO access, which can lead to lower latency for Intel Speed Select handling and also an architectural interface that is said to «persist for several next generations» to ensure the Speed Select Technology is more easily supported across future processors.
For the Intel RAPL code leveraging TPMI’s MMIO interface allows bypassing the existing need of scheduling a thread on the target CPU to read/write and also more unified support across CPU models. Intel RAPL supporting the TPMI interface is said to no longer require any model-specific information.
With the Intel Uncore frequency scaling too, making use of TPMI is expected to avoid all the model-specific handling currently relied upon by the driver.
Sent out this week was this LKML patch series establishing the base Intel TPMI driver that will in turn be used by the various Intel power management driver code moving forward. The patch comments don’t outline when/where TPMI support will premiere, but given that Intel is only now publishing this code and they already wired up RAPL and friends for Sapphire Rapids with the existing implementation, presumably this TPMI feature is being introduced with Emerald Rapids or Granite Rapids — to which Intel engineers have recently begun posting a lot of new EMR/GRR enablement code. With this week’s kernel patches is also the first time I’ve heard of this Intel «TPMI» feature as had Google.